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| 8-BIT RIPPLE COUNTER SY10E137 SY100E137 FEATURES s 1.8GHz min. count frequency s Extended 100E VEE range of -4.2V to -5.5V s s s s s s Synchronous and asynchronous enable pins Differential clock input and data output pins VBB output for single-ended use Asynchronous Master Reset Internal 75K input pull-down resistors Available in 28-pin PLCC packge DESCRIPTION The SY10/100E137 are very high speed binary ripple counters. The two least significant bits were designed with very fast edge rates, while the more significant bits maintain standard ECLinPS output edge rates. This allows the counters to operate at very high frequencies, while maintaining a moderate power dissipation level. The devices are ideally suited for multiple frequency clock generation, as well as for counters in highperformance ATE time measurement boards. Both asynchronous and synchronous enables are available to maximize the device's flexibility for various applications. The asynchronous enable input, A_Start, when asserted, enables the counter while overriding any synchronous enable signals. The E137 features XOR'ed enable inputs, EN1 and EN2, which are synchronous to the CLK input. When only one synchronous enable is asserted, the counter becomes disabled on the next CLK transition. All outputs remain in the previous state poised for the other synchronous enable or A_Start to be asserted in order to re-enable the counter. Asserting both synchronous enables causes the counter to become enabled on the next transition of the CLK. EN1 (or EN2) and CLK edges are coincident. Sufficient delay has been inserted in the CLK path (to compensate for the XOR gate delay and the internal D-flip-flop set-up time) to ensure that the synchronous enable signal is clocked correctly; hence, the counter is disabled. The E137 can also be driven single-endedly utilizing the VBB output supply as the voltage reference for the CLK input signal. If a single-ended signal is to be used, the VBB pin should be connected to the CLK input and bypassed to ground via a 0.01F capacitor. VBB can only source/sink 0.5mA; therefore, it should be used as a switching reference for the E137 only. All input pins left open will be pulled LOW via an input pull-down resistor. Therefore, do not leave the differential CLK inputs open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias regulators and jeopardizing the stability of the device. The asynchronous Master Reset resets the counter to an all zero state upon assertion. PIN CONFIGURATION VCCO Q6 Q7 Q7 Q6 25 24 23 22 21 20 19 18 17 A_Start EN1 EN2 VEE CLK CLK VBB Q5 Q5 26 27 28 1 2 3 4 5 6 7 8 9 10 11 Q4 Q4 VCC Q3 Q3 Q2 Q2 PLCC TOP VIEW J28-1 16 15 14 13 12 Q0 Q1 Q0 VCCO MR Q1 PIN NAMES Pin CLK, CLK Q0-Q7, Q0-Q7 A_Start EN1, EN2 MR VBB VCCO Function Differential Clock Inputs Differential Q Outputs Asynchronous Enable Input Synchronous Enable Inputs Asynchronous Master Reset Switching Reference Output VCC to Output VCCO Rev.: C Amendment: /1 1 Issue Date: February, 1998 Micrel SY10E137 SY100E137 BLOCK DIAGRAM A_Start EN1 EN2 CLK CLK CLK CLK CLK D D MR VBB R D R D R D R CLK Q Q CLK CLK Q Q CLK CLK Q Q CLK CLK Q Q Q D R Q Q0 Q0 Q1 Q1 Q6 Q6 Q7 Q7 SEQUENTIAL TRUTH TABLE(1) Function Reset Count EN1 X L L L H H H H L L L L L L H H H H H L L L X EN2 X L L L L L L L L L L L H H H H H L L L L L X A_Start X L L L L L H H H L L L L L L L L L L L L L X MR H L L L L L L L L L L L L L L L L L L L L L H CLK X Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z X Q7 L L L L L L L L L L L L L L L L L L L L L L L Q6 L L L L L L L L L L L L L L L L L L L L L L L Q5 L L L L L L L L L L L L L L L L L L L L L L L Q4 L L L L L L L L L L L L L L L L L L L L L L L Q3 L L L L L L L L L L H H H H H H H H H H H H L Q2 L L L L L L H H H H L L L L L L H H H H H H L Q1 L L H H H H L L H H L L L L H H L L L L H H L Q0 L H L H H H L H L H L H H H L H L L L H L H L Stop Async. Start Count Stop Sync. Start Stop Count Reset NOTE: 1. Z = LOW-to-HIGH transition 2 Micrel SY10E137 SY100E137 DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol VBB Parameter Output Reference Voltage Input HIGH Current Power Supply Current 10E 100E 10E 100E TA = +25C TA = +85C Max. -1.19 -1.26 150 145 167 A mA -- -- 121 121 145 145 -- -- 121 121 145 145 -- -- 121 139 -- -- Unit V -1.38 -1.38 -- -- -- -- -1.27 -1.35 -1.26 -1.38 150 -- -- -- -- -1.25 -1.31 -1.26 -1.38 150 -- -- -- -- Condition -- Min. Typ. Max. Min. Typ. Max. Min. Typ. IIH IEE AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol fCOUNT tPLH tPHL Parameter Max. Count Frequency Propagation Delay to Output CLK to Q0 CLK to Q1 CLK to Q2 CLK to Q3 CLK to Q4 CLK to Q5 CLK to Q6 CLK to Q7 A_Start to Q0 MR to Q0 Set-up Time (EN1, EN2) Hold Time (EN1, EN2) Reset Recovery Time MR, A_Start Minimum Pulse Width CLK, MR, A_Start Minimum Input Swing (CLK) Com. Mode Range (CLK) Rise/Fall Time, 20% to 80% Q0, Q1 Q2-Q7 TA = +25C TA = +85C Max. -- 2200 2550 3000 3425 3625 4250 4600 4950 1700 1300 -- -- -- -- 1.0 -2.0 400 600 ps ps ps ps V V ps 150 275 -- -- 400 600 150 275 -- -- 400 600 150 275 -- -- -- -- -- -- 1 -- -- Unit MHz ps 1300 1600 1950 2275 2625 2950 3250 3575 950 700 0 300 400 400 0.25 -0.4 1700 2025 2425 2750 3125 3450 3775 4075 1325 1000 -150 150 200 -- -- -- 2150 2500 2925 3350 3750 4150 4450 4800 1700 1300 -- -- -- -- 1.0 -2.0 1300 1600 1950 2275 2625 2950 3250 3575 950 700 0 300 400 400 0.25 -0.4 1700 2050 2450 2775 3150 3475 3800 4125 1325 1000 -150 150 200 -- -- -- 2150 2500 2925 3350 3750 4150 4450 4800 1700 1300 -- -- -- -- 1.0 -2.0 1350 1650 2025 2350 2700 3050 3375 3700 950 700 0 300 400 400 0.25 -0.4 1750 2100 2500 2850 3225 3550 3925 4250 1325 1000 -150 150 200 -- -- -- Condition -- -- Min. Typ. Max. Min. Typ. 1800 2200 -- 1800 2200 Max. Min. Typ. -- 1800 2200 tS tH tRR tPW VPP VCMR tr tf NOTE: 1. Minimum input swing for which AC parameters are guaranteed. Full DC ECL output swings will be generated with only 50mV input swings. PRODUCT ORDERING CODE Ordering Code SY10E137JC SY10E137JCTR SY100E137JC SY100E137JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial 3 Micrel SY10E137 SY100E137 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 4 |
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